The present invention relates to a liquid crystal display, and in particular to a liquid crystal display method and apparatus capable of making a multi-level tone display.
Multi-level tone display methods for conventional liquid crystal display apparatuses will now be described. The first one of such methods is a frame rate control method as described in the above-referenced U.S. Pat. No. 4,808,991 or the application note for HD 66840 LVIC produced by Hitachi, Ltd. The second one of such method is the pulse width modulation method as described in JP-A-59-149393.
The frame rate control method, which is the first method, comprises allotting m frames to one period for liquid crystal display of one dot, and controlling voltage applied in m frames by applying on-voltage to cause activated display in n frames included in the m frames and applying off-voltage to cause inactivated display in m-n remaining frames, multi-level tone display being accomplished visually. The value n/m is referred to as frame rate control ratio. When this value is 0, i.e., display is inactivated in all frames, display luminance level becomes 0%. When the frame rate control ratio is 1, i.e., display is activated in all frames, the display luminance level becomes 100%.
The frame rate control method will now be described by referring to FIGS. 2A-2C, 3A-3C, 4 and 5. FIGS. 2A and 2B are block diagrams of liquid crystal display systems which perform 8-level tone display by using 3-bit display data. FIG. 2C is a waveform diagram showing display pulses applied to the liquid crystal display. FIG. 3A is a block diagram of a frame rate control circuit. FIG. 4 shows display data and frame rate control ratios. FIG. 3B shows display data and frame rate control ratios. FIG. 3C shows how frame rate control is performed for respective frames.
With reference to FIG. 2A, 3-bit display data 5 is converted to frame rate control data FD 10 by a frame rate control circuit 2 shown in FIG. 3A, in response to the output signal of one of frame rate control circuits a125 to h132 selected by a selection circuit 141. In response to the FD 115, either of liquid crystal display puslses P.sub.off 7 and P.sub.on 9 outputted from multi-level tone pulse generation means 13 is selected in a display pulse selection circuit 12 and outputted to a liquid crystal panel 1 as a selected display pulse P11. A liquid crystal display pulse or a pulse which remains at off-level during one horizontal interval as shown in FIG. 2C is used as the P.sub.off 7, whereas a pulse which remains at on-level during one horizontal interval is used as the P.sub.on 9. See, for example, U.S. Pat. No. 3,995,942 or JP-A-50-156396 referenced above.
The frame rate control circuit 2 shown in FIG. 3A includes eight kinds of control circuits 125 to 132. One of frame rate control data outputted therefrom is selected in the selection circuit 141 in accordance with the 3-bit display data 5 and outputted as FD 115. An example of the frame rate control circuits 125 to 132 will now be described by referring to FIGS. 3B and 3C.
FIG. 3B shows display data and frame rate control ratios in HD66840 LVIC produced by Hitachi, Ltd. That is to say, the frame rate control ratio is 0 when the 3-bit display data 5 is (0, 0, 0). When the 3-bit display data is (0, 0, 1), the frame rate control ratio is 1/5. Finally, the frame rate control ratio becomes 1 when the 3-bit display data is (1, 1, 1). These eight ratios ranging from 0 to 1 are assigned to control circuits a125 to h132, respectively. The display state of the liquid crystal panel 1 obtained when (0, 1, 0) or (1, 0, 1) is supplied to this frame rate control circuit 2 as the 3-bit display data 5 is shown in FIG. 3C. When the 3-bit display data 5 is (0, 1, 0), the selected frame control rate is 1/3. That is to say, three frames are chosen as one period and only one of the three frames becomes the on-state whereas two remaining frames become the off-state. In the frame rate control circuit 2, the control circuit C127 is selected and its output is sent out as FD 115. In the display pulse selection circuit 12, the P.sub.off 7 or P.sub.on 9 is selected by the FD 10. In the first frame of the three frames forming one period, the P.sub.on 9 is selected and display of luminance level 100% is performed. In the second and third levels, the P.sub.off 7 is selected and display of luminance level 0% is performed. An average of the three frames is just equivalent to display of luminance level 33.3%. When the 3-bit display data 5 is (1, 0, 1), a frame rate control ratio of 4/5 is selected in the same way. Five frames are thus chosen as one period, and the P.sub.on 9 is supplied to four frames out of the five frames whereas the P.sub.off 7 is supplied to one remaining frame. An average of these five frames becomes just equivalent to display of luminance level 80%.
The above described example of the prior art will now be described from a different viewpoint by referring to FIGS. 2B and 3A as well as FIG. 4 which shows an example of frame rate control data.
With reference to FIG. 2B, 3-bit display data 114 is converted to frame rate control data FD 115 by a frame rate control circuit 104 shown in FIG. 3A. In accordance with this FD 115, a liquid crystal display pulse P.sub.off (i.e., a pulse which is at the off-level during one horizontal interval) or P.sub.on (i.e., a pulse which is at the on-level during one horizontal interval) is outputted from an X drive circuit 102 to a liquid crystal panel 101. See, for example, U.S. Pat. No. 4,808,991.
The frame rate control circuit 104 shown in FIG. 3A has eight kinds of control circuits 125 to 132. One of frame rate control data 133 to 140 outputted from those control circuits is selected in a selection circuit 141 in accordance with the 3-bit display data 114 and outputted as the FD 115. Each of the control circuits 125 to 132 generates frame rate control data complying with the frame rate control ratio by using a leading line clock 116, a line clock 117 and a data latch clock 119. In a scheme used in the above described HD66840 LVIC, all dots forming the liquid crystal panel are not subject to frame rate control at the same timing, but n lines are removed out of in lateral lines forming one unit in order to prevent flicker on the screen of the liquid crystal panel 101. Frame rate controlled data are thus generated by using the leading line clock 116 and the line clock 117.
FIG. 4 shows frame rate control data of the HD66840 LVIC produced by Hitachi, Ltd. under the condition that the frame rate control ratio is 4/5. In shaded regions, display is in the on-state. When the frame rate control ratio is 4/5, multi-level tone display is accomplished by defining five lateral lines as one unit, introducing four lateral lines among five lateral lines in the display on state, and moving activated display lines and inactivated display lines every frame.
The pulse width modulation method which is the above described second method will now be described by referring to FIGS. 5, 6A and 6B.
FIG. 5 shows an example of configuration of a liquid crystal display apparatus which accomplishes three-level tone display by using the pulse width of the voltage pulse applied to the liquid crystal apparatus in one horizontal interval. Either of two kinds of data 122 and 123 of display information XA and XB for displaying one dot of the liquid crystal apparatus in one horizontal internal is selected in a data selector 112 by a data select signal 121. A selected data 124 is supplied to an X drive circuit 102 as data XD of one kind. The X drive circuit 102 takes in the data XD supplied from the data selector 112 in response to a data latch clock 119. This taking-in operation is repeated until display data corresponding to one line have been taken in. Thereafter, the X drive circuit 102 outputs liquid crystal application pulses onto signal lines X1, X2, --, Xi in response to a pulse clock 118. The pulse clock 118 is obtained by uniformly dividing pulses of the line clock 117 every horizontal interval into two. A Y drive circuit 103 takes in a leading line clock 116 in response to the line clock 117 to produce a "high" state on a line Y1, and in response to successive pulses of the line clock 117, it shifts the "high" state successively to Y2, --, Yj. A liquid crystal panel 101 is an i-row by j-column matrix panel. Liquid crystal application pulses X1, X2, --, Xi outputted from the X drive circuit 102 are applied to liquid crystal cells connected to "high" state lines among output lines Y1, --, Yj of the Y drive circuit 103, display being thus effected.
FIG. 6A shows liquid crystal application pulses outputted from the X drive circuit 102. In one horizontal interval, either of two kinds of display data XA and XB is transmitted from the data selector 112 to the X drive circuit 102 as display data XD every half of the horizontal interval. In response to the data XD, one out of four kinds of pulses, i.e., pulse 1 to pulse 4, is selected and outputted from the X drive circuit 102.
FIG. 6B shows correspondence between the display data XD and the drive pulse outputted from the X drive circuit 102.
When display data are represented as (XA, XB)=(0, 0), the X drive circuit 102 outputs pulse 1 as a liquid crystal application pulse and a display dot is inactivated as shown in FIG. 6B. When (XA, XB)=(1, 1), the liquid crystal application pulse becomes pulse 4 and a display dot is activated. When (XA, XB)=(0, 1), or (1, 0), the liquid crystal application pulse becomes pulse 3 or pulse 2, respectively, producing a half tone display between active and inactive dots in both cases. The luminance (transmission factor) of the liquid crystal is dependent on the effective value of the voltage applied to it. Since the pulse clock 118 is obtained by equally splitting or dividing the line clock 117, the pulse 2 and the pulse 3 have an equal "H" period and thus an equal effective value. Consequently, the pulse 2 and pulse 3 provide an equal luminance of liquid crystal, which is an intermediate luminance between an active dot and inactive dot, resulting in the accomplishment of three-level tone display.
In the liquid crystal display apparatus shown in FIG. 5, therefore, tone display can be accomplished by varying the effective value of the voltage applied to the liquid crystal panel 101 through the combination of display data XA and XB.
If the period of frame rate control, i.e., the value of m is increased in the above described frame rate control method of the prior art, timing of frame rate control is visually recognized. That is to say, flicker or display float is incurred, resulting in degraded quality of tone display. Therefore, the number of practical tone levels is limited to about ten. Multi-level tone display such as 16-level tone display or 32-level tone display cannot be accomplished without degrading the display quality.
On the other hand, the pulse width modulation method of the prior art has a problem that in case the display area of half tone display is large in the X direction (i.e., in the lateral direction of the screen) noise is created by rising edges or falling edges of pulses which make simultaneous transition in one horizontal interval, resulting in degraded luminance of display.
In case the display area of half tone display is large in the Y direction (i.e., in the longitudinal direction of the screen), the frequency component of the liquid crystal application pulse is raised, resulting in problems of lowered luminance of display and increased crosstalk. JP-A-2-1812 laid open Jan. 8, 1990 discloses a related art, but is not prior art.